Cleared FPGA Designer with Security Clearance

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Job description

A Global Government Contracting Company is seeking multiple FPGA Designers mid - principal level to join their team in Salt Lake City, UT! This will be a 9/80 schedule and 100% onsite. You must have a final DoD secret clearance! Responsibilities:
• RTL Design, implementation, validation, system integration, and support of high-speed digital FPGA designs in compliance with written specifications within a DoD process controlled work environment.
• Assist with bids, proposals, specification creation and updates, and participate in code and design reviews.
• FPGA verification through simulation and unit testing. Lead projects successfully, with an emphasis on efficiency and positive team management.
• Present information effectively to multiple audiences.
• Manage complicated development schedules.
• Analyze and enhance the efficiency, stability, and scalability of system resources.
• Integrate and validate new product designs.
• Provide production support. Additional Skills:
Experience and/or education should include:
• Forward Error Correction (FEC)
• Modulation
• Demodulation
• Digital filters
• Industry standard interfaces (e.g., 10/100/1000 Ethernet, SPI, UART, SDRAM, DDR3, JESD, PCIe, Ethernet).
• Networking
• FPGA verification through simulation and unit testing.
• A GPA of 3.0 or higher in post-secondary education work (3.5 preferred)
• Ability to design, implement, validate, integrate, and support high speed digital FPGA designs in compliance with written specifications within a DoD process-controlled work environment
• The following qualifications are preferred, but not required:
• Expertise in either VHDL (preferred) or Verilog development languages
• Experience implementing complex modem and/or DSP circuits in programmable logic using FPGA devices. Equivalent experience in ASIC design is also applicable.
• Expertise in FPGA simulation, synthesis, and placement software tools such as ModelSim/QuestaSim, Synplify, Xilinx Vivado and/or Client Quartus development tool sets
• Networking protocol experience
• Expertise in laboratory debug techniques using digital scopes, logic analyzers, BERTS, and other complex measurement devices
• Experience with FPGA timing closure
• FPGA Design using High-speed serial interfaces (3+ Gbps)
• Working knowledge of signal processing, control systems, digital video/audio, networking, TCP/IP/UDP, wireless communications and reading hardware schematics
• Familiarity with code revision management tools such as Git/Clearcase
• Familiarity with C/C++/C# and Matlab/Simulink

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